Yeah that tracks, looking at all the different submitted M3 GB5 scores, about a 1-5% overall IPC increase (more for some subtest, less for others) depending, similar for the M3 to M2.
============
Although, I do feel the need to point out again though, a problem with the "IPC" argument at different clocks speeds is that the same processor clocked x% higher isn't guaranteed to get an x% increase in performance - i.e. IPC tends to get lower with higher clocks as things like cache misses, RAM latency, etc ... all come into play the more you increase the clocks and thus sometimes all you do is increase the number of cycles a processor is waiting. For instance, take Horizon Detection. As @theorist9 noted it looks like a slight IPC regression and that may be the case. This is for the Intel chip Geekbench uses as a reference, looking at the L3 cache miss and the working data set we see a lot of trips to main memory if the requested data isn't in L1-3, more than most of the other tests (a few others match it or exceed it). Not being able to measure the latency difference between M4 and M3's RAM I can't necessarily say that's the sole cause of an IPC decrease, but you could see how it could be for such a test (the test also has a really high branch miss rate in that Intel chip, though of course an Apple chip has a completely different branch predictor, and it has overall low IPC compared to other tests, so it's possibly a combination of factors).
Don't get me wrong, I'd love to have clockspeed increases AND IPC increases at those higher clocks, but more important is performance per watt. Further, the same (or similar) IPC at higher clocks but same or similar power doesn't mean the architecture is staying still. In fact, we know it isn't, so this isn't just TSMC's node or increased power. True, it does mean that outside of the introduction of specialty hardware like SME, SVE2, etc ... and optimizations to take advantage of those (which is still important! and yes still counts, so yes we got nice IPC uplift for any application that can take advantage of SME ... like say stockfish!
), we aren't getting massive leaps in single core performance beyond clock speed. The architectural changes are likely what's letting Apple keep IPC up with clocks. And that in and of itself is interesting. It suggests that massive IPC increases in "normal" code for "normal" floating point and integer workloads is getting harder for Apple's wide CPU design. At least Apple hasn't managed it in four (or 5 counting iPhones) generations. So eventually others may catch up in IPC, but then so far the only way people have found to do so is in making wider cores so they'll likely start hitting the same limits unless someone figures out where the bottleneck to further gains is and solves it (if it can be solved).
Last edited:
