In the light of recent reports that cache SRAM does not benefit as much from node size improvements as logic, I was wondering about the feasibility of moving the cache to a separate bonded die, like AMD is now pioneering with their V-cache CPUs. For example, Apple could have fitted 16 more GPU cores on the M2 Max die if the SLC cache were moved to a separate chip. But from what I understand, die-to-die connection, even for directly bonded dies comes at a cost of added energy consumption. Does anyone know how much energy loss are we talking about compared to on-chip caches? Is it something that can be used on an energy-efficient laptop or would it disproportionately increase idle power consumption?