Overview from Anandtech:
Solid gains of 15-18% IPC, but we’ll see what actually gets implemented. I haven’t followed recently so I don’t know if it’s still a problem but implementation would sometimes suffer compared to “paper performance” - e.g. historically ARM would design cores with a range of possible cache sizes but Qualcomm et al would always go on the smaller side of cache, hurting performance on high end cores.
Will be interesting to see how they compare to Apple’s current generation offerings as well as its next generation of A/M processors.
Solid gains of 15-18% IPC, but we’ll see what actually gets implemented. I haven’t followed recently so I don’t know if it’s still a problem but implementation would sometimes suffer compared to “paper performance” - e.g. historically ARM would design cores with a range of possible cache sizes but Qualcomm et al would always go on the smaller side of cache, hurting performance on high end cores.
Will be interesting to see how they compare to Apple’s current generation offerings as well as its next generation of A/M processors.