Today's Apple event

leman

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I go by the cache blocks (big rectangles) and look at the structures around them. When you know how many cores there are, you can pick them out by counting. The E-cores are around the smallest cache block (a square-ish shape, usually), and to me they look larger in the M3-series – probably not half, but more than a quarter.

Did I identify the cores correctly? I got the ratio of approximately 1/4, which is consistent to the A17 annotations I linked earlier.

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Joelist

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M3 looks pretty cool. I expect they are tailoring the bus more closely to what their testing has showed to be the maximum load. The RAM splits are a little odd - 8/18/36. I would have expected 8/16/32 on the notion that these are standard chips but this suggests something a little different is in play.
 

theorist9

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Memory configuration is so weird this time around. If you select M3 16 CPU cores + 40 GPU cores the base RAM is 48GB (good), and you can select 64GB or 128GB, but not 96GB, as that configuration is reserved for the 16 CPU + 30 GPU M3 Max 😵‍💫
Based on the bandwidth numbers @theorist9 posted just above this, they must be populating 3/4 of the M3 Max memory channels on the 14cpu/30gpu chips. This makes sense: if 400 GB/s is adequate to feed the full 40-core GPU (which is the biggest bandwidth monster in the system), then 300 GB/s should be good enough for the 30-core.
Yes, and that would also explain the seemigly odd memory configurations. They're probably using three physical memory modules on the base Max, and four on the high-end one, in combination with module sizes of 12 GB, 16 GB, and 32 GB:

Base Max: {36 GB, 96 GB}/(3 modules) = {12 GB/module, 32 GB/module}
High Max: {48 GB, 64 GB, 128GB}/ (4 modules) = {12 GB/module, 16 GB/module, 32 GB/module}

It seems they decided to forgo the 3 modules x 16 GB/module = 48 GB SKU for the base Max.
 
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dada_dave

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M3 looks pretty cool. I expect they are tailoring the bus more closely to what their testing has showed to be the maximum load.

I agree that if testing reveals that the compute bandwidth of each chip is well served by the memory bandwidth, then there’s no problem. I think people are more concerned about this because in testing the reduced memory bandwidth on some of the Nvidia chips definitely impacted performance.

The RAM splits are a little odd - 8/18/36. I would have expected 8/16/32 on the notion that these are standard chips but this suggests something a little different is in play.
I think @leman, @theorist9, and @mr_roboto in posts above have the right sense of it. The result is definitely odd though.
 
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dada_dave

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FWIW, Chips and Cheese just posted this analysis of the M2 GPU:
Thanks for the article! Really interesting to read about what Apple does well and where seemingly they can improve. I agree that, for now, the benefits of Apple’s approach may be unique to Apple, but depending on the advancement of packaging technologies may not always be the case, more companies may be able to take advantage of the approach.
 

theorist9

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Thanks for the article! Really interesting to read about what Apple does well and where seemingly they can improve. I agree that, for now, the benefits of Apple’s approach may be unique to Apple, but depending on the advancement of packaging technologies may not always be the case, more companies may be able to take advantage of the approach.
I thought it would be interesting to post here because it appears to be a sophisticated treatment, and I was curious to hear a "peer review" of their analysis from the site experts.
 
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