M1 Ultra - Ultra fusion interconnect

[tomO2013]

Hi Guys,

So just done watching the apple keynote.
The M1 Ultra looks incredible from a performance/watt/form factor perspective - it’s a real bloody nose to Intel when you factor the form factor that is providing such performance.

Probably the most interesting part of this chip to me is the ‘Ultra Fusion’ interconnect technology (2.5TB/s - (total combined? or 2.5 TB/s each way??) we will need to wait and see I guess.

Obviously we are scant on the more technical nuanced details right now. I’m also interested to speculate now whether Apple will have increased the core frequency for a desktop part (unlikely IMHO, but anything is possible).

@Cmaier I’d love to get your take on this interconnect and thoughts having seen the presentation.

T

 

[Cmaier]

Hi Guys,

So just done watching the apple keynote.
The M1 Ultra looks incredible from a performance/watt/form factor perspective - it’s a real bloody nose to Intel when you factor the form factor that is providing such performance.

Probably the most interesting part of this chip to me is the ‘Ultra Fusion’ interconnect technology (2.5TB/s - (total combined? or 2.5 TB/s each way??) we will need to wait and see I guess.

Obviously we are scant on the more technical nuanced details right now. I’m also interested to speculate now whether Apple will have increased the core frequency for a desktop part (unlikely IMHO, but anything is possible).

@Cmaier I’d love to get your take on this interconnect and thoughts having seen the presentation.

T

I think I posted a little bit about my conjecture re: the ultrafusion interconnecT. To my eyes it looks like a synchronous crossbar or something, and not like a bus. That would also get you the performance, at the cost of not being easily expandable to higher numbers of die (you’d need some sort of smart interposer to do that). But tough to guess without a tear down that shows it in more details. Very impressive, for sure, though.

 

[chengengaun]

The M1 Ultra transistor count is exactly twice that of M1 Max - 114 billion vs 57 billion - is the UltraFusion structure already built into M1 Max but not used?

 

[Cmaier]

The M1 Ultra transistor count is exactly twice that of M1 Max - 114 billion vs 57 billion - is the UltraFusion structure already built into M1 Max but not used?

View attachment 12320

Yes.

 

[tomO2013]

They mentioned graphics being able to use up to 64GB unified memory on the 128GB variant of the Ultra during the keynote (if I recalled correctly).

I wonder if this limit is driven by affinity to a single die where the per die limit RAM limit is 64GB … it didn’t appear to be an arbitrary number.

 

[quarkysg]

They mentioned graphics being able to use up to 64GB unified memory on the 128GB variant of the Ultra during the keynote (if I recalled correctly).

I must have missed this part, cause I don't seem to remember such a limitation mentioned for the M1 Ultra.

If true, it would be a big mistake on Apple's part tho. The GPU cores, like all other SoC cores, should be able to grab as much free memory as possible.

 

[mr_roboto]

They mentioned graphics being able to use up to 64GB unified memory on the 128GB variant of the Ultra during the keynote (if I recalled correctly).

I wonder if this limit is driven by affinity to a single die where the per die limit RAM limit is 64GB … it didn’t appear to be an arbitrary number.

I think you must have misheard something, as that just isn't how their system architecture works. They emphasized several times that their interconnect technology allows two M1 Maxes to behave like a single large SoC with fully unified memory as far as software is concerned. One of their senior graphics driver managers tweeted this:

https://www.twitter.com/i/web/status/1501279361965518849/

This means you don't write software as if M1 Ultra has two GPUs. As far as software authors are concerned, it has just one giant 48 core or 64 core GPU. That wouldn't work if the graphics cores on die A couldn't access memory connected to die B, and vice versa - everything has to have access to everything.

 

[tomO2013]

I’m so sorry, please ignore my post, I’m completely wrong and misheard.

Checked the apple press release

Apple unveils M1 Ultra, the world’s most powerful chip for a personal computer

Apple today announced M1 Ultra, the next giant leap for Apple silicon and the Mac.

www.apple.com

There was no mention of an addressable memory limit on the ultra for graphics.

 

[Andropov]

There was no mention of an addressable memory limit on the ultra for graphics.

There probably is some limit, though. The 64GB Max can't fill more than 48GB as Metal buffers.

 

[Cmaier]

They mentioned graphics being able to use up to 64GB unified memory on the 128GB variant of the Ultra during the keynote (if I recalled correctly).

I wonder if this limit is driven by affinity to a single die where the per die limit RAM limit is 64GB … it didn’t appear to be an arbitrary number.

That’s not what i heard. They said 64GB for the max, and 128gb for the ultra.

 

[Andropov]

That’s not what i heard. They said 64GB for the max, and 128gb for the ultra.

Yep. Timestamp 42:30 on the keynote video. They are, however, very ambiguous on the wording. They're talking about dedicated graphics card video memory and suddenly jump to 'with M1 Max you can access to up to 64GB of unified memory, and with M1 Ultra you can [access to] up to 128GB of unified memory'. With what? The GPU only? I assume that's what they mean, but it's a bit vague.

 

[Cmaier]

Yep. Timestamp 42:30 on the keynote video. They are, however, very ambiguous on the wording. They're talking about dedicated graphics card video memory and suddenly jump to 'with M1 Max you can access to up to 64GB of unified memory, and with M1 Ultra you can [access to] up to 128GB of unified memory'. With what? The GPU only? I assume that's what they mean, but it's a bit vague.

In apple’s unified model its understood that both the CPUs and the GPU can access the full memory, so that’s how I understand what was said.

 

[jbailey]

In apple’s unified model its understood that both the CPUs and the GPU can access the full memory, so that’s how I understand what was said.

Any knowledge of CXL? I saw a post on Ars that speculated that the ASi Mac Pro is likely to use CXL to solve both memory and IO issues with Apple's silicon architecture. I might dig into the spec but I don't really have time right now. It looks interesting though.

 

[Cmaier]

Any knowledge of CXL? I saw a post on Ars that speculated that the ASi Mac Pro is likely to use CXL to solve both memory and IO issues with Apple's silicon architecture. I might dig into the spec but I don't really have time right now. It looks interesting though.

I would doubt they use CXL. It looks to me more like simply a direct point-to-point style connection fabric.

 

[Colstan]

I'm not going to pretend to know what I'm looking at, but this supposed leaker, which I have never heard of, claims to have schematics of what Apple will use to connect two Ultras in the new Mac Pro. I figured I'd run it by @Cmaier and everyone here, just in case it might mean something.
https://www.twitter.com/i/web/status/1502675792886697985/

 

[Cmaier]

I'm not going to pretend to know what I'm looking at, but this supposed leaker, which I have never heard of, claims to have schematics of what Apple will use to connect two Ultras in the new Mac Pro. I figured I'd run it by @Cmaier and everyone here, just in case it might mean something.
https://www.twitter.com/i/web/status/1502675792886697985/

Yeah, that’s just a pin-out. You can’t see what’s in those white rectangles. But note how tall they are - that’s bigger then the reticle, so that can’t be a single piece of silicon. So either it’s two pieces of silicon (doubtful, or they would have shown the interconnect between them), or it’s something that happens on the substrate - in other words, it isn’t a die, but it’s some sort of package-level interconnect. But if it’s package-level interconnect, it simply won’t work - there’s nothing for it to connect to in Ultra that would enable it to work.

So I think it’s nothing.

 

[Colstan]

But if it’s package-level interconnect, it simply won’t work - there’s nothing for it to connect to in Ultra that would enable it to work.

So I think it’s nothing.

Thanks for the answer. Of course, Vadim from Max Tech had to make an appearance. We need not worry, he's on the case, so I'm sure we'll have an answer shortly. I appreciate his energy when making videos, the comparison bakeoffs are actually useful, but as @leman says, Max Tech is "barely incompetent".

 

[Cmaier]

Also: codename DaisyXL, while the interconnect between the Max’s is Daisy1 or Daisy2. This implies it’s the same sort of deal. That won’t work. Nothing for it to connect to.

 

[Andropov]

I'm kinda surprised by how many rumours are calling a 4-die M1 Ultra. Almost to the point to make me doubt. But as @Cmaier says, there's just nowhere to connect them.

 

[Cmaier]

I'm kinda surprised by how many rumours are calling a 4-die M1 Ultra. Almost to the point to make me doubt. But as @Cmaier says, there's just nowhere to connect them.

Yeah, unless that strip has logic in it that can play traffic cop and make each ultra think it is only talking to one other ultra. And even then you couldn’t double up the RAM. But all the rumors make that strip look like it’s just wires.