Thread: iPhone 15 / Apple Watch 9 Event

exoticspice1

Site Champ
Posts
300
Reaction score
103
Also guys this is the first time Apple did not name their CPU cores. Instead we take the codename of the SoC which is Coll.

Geekerwan referred to the P core as Coll. So Apple has not named the P cores like it did for previous P cores of the A series chips.

This is also not a Everest core because of the 9 wide decoder. Looks like M3 will help answer these questions


Is the low memory bandwidth we are talking about referring to the LPDDR5 RAM?
Because I remeber the type and speed of RAM also plays a huge part in CPU performance like Intel's Raptor lake and Zen chips.
 

Altaic

Power User
Posts
145
Reaction score
181
Also guys this is the first time Apple did not name their CPU cores. Instead we take the codename of the SoC which is Coll.

Geekerwan referred to the P core as Coll. So Apple has not named the P cores like it did for previous P cores of the A series chips.

This is also not a Everest core because of the 9 wide decoder. Looks like M3 will help answer these questions


Is the low memory bandwidth we are talking about referring to the LPDDR5 RAM?
Because I remeber the type and speed of RAM also plays a huge part in CPU performance like Intel's Raptor lake and Zen chips.
Coll is an island in Scotland; not sure if that’s consistent enough for you. Seems like a nice spot to me 🤷‍♂️

Regarding memory bandwidth, it’s actually more about memory latency (which I had previously and foolishly dismissed). I’ll try to follow up on that and a couple of other things soon.

@leman Any chance you could share your benchmark code (or alternatively & ideally a TestFlight build)? I think it’d be really interesting to flesh out your plots with the A15, A16, and M2.
 

dada_dave

Elite Member
Posts
2,193
Reaction score
2,197
Coll is an island in Scotland; not sure if that’s consistent enough for you. Seems like a nice spot to me 🤷‍♂️

Regarding memory bandwidth, it’s actually more about memory latency (which I had previously and foolishly dismissed). I’ll try to follow up on that and a couple of other things soon.
For what we’re talking about, single core/IPC, yes as you say it is more about latency. It can be about bandwidth/memory level parallelism too though. I remember, and this effect may be what @exoticspice1 is referring to, when Alder Lake first came out and it straddled DDR4 vs DDR5, obviously the multicore results were massively different and that would be primarily down bandwidth being better on DDR5. However, interestingly latency actually went up for DDR4 to 5! (By a very small margin) but most ADL single core SPEC results were still better on DDR5 except for the one or two of those that were memory latency bound. They were still more sensitive to bandwidth than latency at the single core (though again the latency change was small and the bandwidth gain was big - do something more radical like @theorist9 was suggesting and replace DDR with GDDR and I don’t think this would hold true).



 

leman

Site Champ
Posts
659
Reaction score
1,220
@leman Any chance you could share your benchmark code (or alternatively & ideally a TestFlight build)? I think it’d be really interesting to flesh out your plots with the A15, A16, and M2.

I'd prefer not to do TestFlight because of anonymity and also because it's much more work. My code is really only bare-bones and the results are printed to stdout. ButI'd be happy to upload the project and the data to GitHub. Will try to find some time over the weekend.
 

Jimmyjames

Site Champ
Posts
697
Reaction score
796
@leman afaik you are the only one on this thread with a new iPhone 15 Pro. It’s early to say, but do you have any comments on your experience with battery life, or overheating. I have seen some reports of the phone having to cool down during setup. That doesn’t sound great.
 

Cmaier

Site Master
Staff Member
Site Donor
Top Poster Of Month
Posts
5,398
Reaction score
8,659
Also guys this is the first time Apple did not name their CPU cores. Instead we take the codename of the SoC which is Coll.

Geekerwan referred to the P core as Coll. So Apple has not named the P cores like it did for previous P cores of the A series chips.

This is also not a Everest core because of the 9 wide decoder. Looks like M3 will help answer these questions


Is the low memory bandwidth we are talking about referring to the LPDDR5 RAM?
Because I remeber the type and speed of RAM also plays a huge part in CPU performance like Intel's Raptor lake and Zen chips.
Apple named the cores. They just didn’t tell anyone the names (yet). We always name our work. Sometimes, unfortunately, the marketing teams come up with their own names. Usually I had no idea which thing was which - I work on a chip we call “chomper p” and marketing calls it something stupid like “river glen” and then somebody in the public asks me about that chip and I don’t know which one it is. Fucking marketing team.

I’m sorry, did someone say something?
 

leman

Site Champ
Posts
659
Reaction score
1,220
@leman afaik you are the only one on this thread with a new iPhone 15 Pro. It’s early to say, but do you have any comments on your experience with battery life, or overheating. I have seen some reports of the phone having to cool down during setup. That doesn’t sound great.

It can get warm to touch during demanding use (e.g. benchmarks), but not as bad as my partner’s 12 Pro. As to battery life, I got it about 26 hours ago, didn’t charge it (except for the few minutes it was connected to my laptop to enable dev mode); ant it still has 40% battery left. That’s after updating, migrating data, a series of benchmarks, and some internet use today. Seems better than I ever got from an iPhone. But again, purely subjective. I don’t have the tools or the knowledge to do proper battery tests.
 

Nycturne

Elite Member
Posts
1,142
Reaction score
1,494
@leman afaik you are the only one on this thread with a new iPhone 15 Pro. It’s early to say, but do you have any comments on your experience with battery life, or overheating. I have seen some reports of the phone having to cool down during setup. That doesn’t sound great.

Mine did get warm during setup, but didn’t trigger or hit any limits. With a case and wallet attached.

I wasn’t charging while doing setup though.
 

Andropov

Site Champ
Posts
635
Reaction score
809
Location
Spain
Apple named the cores. They just didn’t tell anyone the names (yet). We always name our work. Sometimes, unfortunately, the marketing teams come up with their own names. Usually I had no idea which thing was which - I work on a chip we call “chomper p” and marketing calls it something stupid like “river glen” and then somebody in the public asks me about that chip and I don’t know which one it is. Fucking marketing team.
A couple WWDC's ago I got to talk with an Apple engineer from the Metal team to look over the rendering performance I was getting in an app of mine, and while looking at the metal frame capture output together I asked about the max bandwidth of the device I was using (A15 Bionic), because the render appeared to be bandwidth-limited in the frame capture, but I didn't know if the bandwidth memory figure I was seeing could be improved in some way (more coherent accesses...) or if the device was just reaching it's maximum bandwidth and there was nothing I could do about it.

He just casually commented that he'd need to look up what the internal codename for the iPhone 13 Pro / A15 Bionic was because he remembered the bandwidth figures of the chips but not the official names of the SoC 😂
 

Jimmyjames

Site Champ
Posts
697
Reaction score
796
It can get warm to touch during demanding use (e.g. benchmarks), but not as bad as my partner’s 12 Pro. As to battery life, I got it about 26 hours ago, didn’t charge it (except for the few minutes it was connected to my laptop to enable dev mode); ant it still has 40% battery left. That’s after updating, migrating data, a series of benchmarks, and some internet use today. Seems better than I ever got from an iPhone. But again, purely subjective. I don’t have the tools or the knowledge to do proper battery tests.
Thanks. Sounds great.
 

Cmaier

Site Master
Staff Member
Site Donor
Top Poster Of Month
Posts
5,398
Reaction score
8,659
A couple WWDC's ago I got to talk with an Apple engineer from the Metal team to look over the rendering performance I was getting in an app of mine, and while looking at the metal frame capture output together I asked about the max bandwidth of the device I was using (A15 Bionic), because the render appeared to be bandwidth-limited in the frame capture, but I didn't know if the bandwidth memory figure I was seeing could be improved in some way (more coherent accesses...) or if the device was just reaching it's maximum bandwidth and there was nothing I could do about it.

He just casually commented that he'd need to look up what the internal codename for the iPhone 13 Pro / A15 Bionic was because he remembered the bandwidth figures of the chips but not the official names of the SoC 😂

To this day, I have no idea what the official name of the chip I worked on at Sun was. I don’t even know if that thing shipped - it was clearly going to be a disaster so I got out of there fast. It may have been UltraSparc V (eventually) but they cancelled it and I am not sure if any shipped. Think it taped out, though,
 

Aaronage

Power User
Posts
144
Reaction score
213
I managed to pass 3000 points in Geekbench 6 with my iPhone 15 Pro 🤩


Airplane mode, no “running” apps and… an ice pack 😜
I should add also - the phone was fully charged and connected to an external power bank, so it was running from an external power source and the internal battery was cold.

I wish I had a way of measuring power drawn from the power bank. Given what we’re learning about the power characteristics of A17 Pro, I’m curious how much it uses when unconstrained thermally 😅
 

theorist9

Site Champ
Posts
618
Reaction score
573
It’s good. What’s a little odd is that based on this we should be seeing higher IPC improvements than what early benchmarks are showing. Could be that memory bandwidth is not high enough, or something else is going on. But I suspect the core design is really intended for M3, and we will see IPC gains in M3 more commensurate with the increase in data path width and ROB increases.
Not sure how Dougall identified these features, but is it possible they are physically there but not fully utilized by the the iPhone A17's firmware, and are instead being held in reserve for use on the larger iPads (where performance is more important, and thermals less of a concern)?

And just for fun, some blue-sky speculation (no pun intended): At least some of these features seem like they could be used to implement a more agressive speculative execution strategy. The risk/reward ratio for speculative execution could be higher on the iPhones than the iPads (more risk if the iPhones are more targeted, less reward because the iPhones don't benefit as much from an increase in speed). Thus I'm wondering if Apple is not making full use of these additional features on the iPhone's A17 because it decided to implement a less agressive set of speculative execution strategies on the iPhone than on the on the iPad; if so, that would result in less IPC improvement for the former.

Of course, the same could also apply to the M3 vs. the A17: More agressive speculative execution => greater IPC.
 
Last edited:

Cmaier

Site Master
Staff Member
Site Donor
Top Poster Of Month
Posts
5,398
Reaction score
8,659
Not sure how Dougall identified these features, but is it possible they are physically there but not fully utilized by the the iPhone A17's firmware, and are instead being held in reserve for use on the larger iPads (where performance is more important, and thermals less of a concern)?

And just for fun, some blue-sky speculation (no pun intended): At least some of these features seem like they could be used to implement a more agressive speculative execution strategy. The risk/reward ratio for speculative execution could be higher on the iPhones than the iPads (more risk if the iPhones are more targeted, less reward because the iPhones don't benefit as much from an increase in speed). Thus I'm wondering if Apple is not making full use of these additional features on the iPhone's A17 because it decided to implement a less agressive set of speculative execution strategies on the iPhone than on the on the iPad; if so, that would result in less IPC improvement for the former.

Of course, the same could also apply to the M3 vs. the A17: More agressive speculative execution => greater IPC.
The speculative execution features would be in the CPU core - the scheduler/reservation stations. Wouldn’t be something that would likely be disabled, since the cost of turning it on is low. (And you really don’t design these things to be disabled or throttled back. About the only way to “throttle” it would be to disable part of the reservation stations or something, and there would be no point in it. Wouldn’t save any power.). If they are there, Apple would use them. I still lean toward memory bottleneck (as someone who has way too little information to really know at this point).
 

theorist9

Site Champ
Posts
618
Reaction score
573
The speculative execution features would be in the CPU core - the scheduler/reservation stations. Wouldn’t be something that would likely be disabled, since the cost of turning it on is low. (And you really don’t design these things to be disabled or throttled back. About the only way to “throttle” it would be to disable part of the reservation stations or something, and there would be no point in it. Wouldn’t save any power.). If they are there, Apple would use them. I still lean toward memory bottleneck (as someone who has way too little information to really know at this point).
IIUC, latency is difficult to estimate because it depends on a complex set of timings. But, FWIW, in 2021 Micron claimed that, under "heavy loading", its 7500 MHz LPDDR5x would offer a 20% latency reduction over 5500 MHz LPDDR5. I don't know what the corresponding reduction would be if, with M3, Apple goes to 8533 MHz LPDDR5x from its current 6400 MHz LPDDR5, or how much that would impact any latency bottlenecks present in the current A-series design. [Though that change would give a 8533/6400 – 1 = 33% increase in bandwidth.]

1695505923617.png
 
Top Bottom
1 2